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STK16C88-3
32K x 8 AutoStorePlusTM nvSRAM 3.3V QuantumTrapTM CMOS Nonvolatile Static RAM
FEATURES
* Transparent Data Save on Power Down * Internal Capacitor Guarantees AutoStoreTM Regardless of Power-Down Slew Rate * Directly Replaces 32K x 8 Static RAM, BatteryBacked RAM or EEPROM * 35 Access Time * STORE to Nonvolatile Elements Initiated by Software or AutoStorePlusTM * RECALL to SRAM Initiated by Software or Power Restore * 10mA Typical ICC at 200ns Cycle Time * Unlimited READ, WRITE and RECALL Cycles * 1,000,000 STORE Cycles to Nonvolatile Elements (Commercial/Industrial) * 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) * Single 3.3V + 0.3V Operation * Commercial and Industrial Temperatures * 28-Pin PDIP Package BLOCK DIAGRAM
QUANTUM TRAP 512 x 512 VCC STORE/ RECALL CONTROL
DESCRIPTION
The STK16C88-3 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down. An internal capacitor guarantees the STORE operation regardless of power-down slew rate. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAM inputs. The STK16C88-3 is pin-compatible with 32k x 8 SRAMs and battery-backed SRAMs, allowing direct substitution while providing superior performance. The STK14C88-3, which uses an external capacitor, is also available.
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
A5 A6 A7 A8 A9 A11 A12 A13 A14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
STORE STATIC RAM ARRAY 512 x 512 RECALL
POWER CONTROL
INTERNAL CAPACITOR
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
ROW DECODER
28 - 600 PDIP
INPUT BUFFERS
COLUMN I/O COLUMN DEC SOFTWARE DETECT A0 - A13
PIN NAMES
A0 - A14 W Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 3.3V) Ground
A0 A1 A2 A3 A4A10
DQ0 - DQ7
G E W
E G VCC VSS
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STK16C88-3
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 4.5V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1b ICC2
c
(VCC = 3.0V-3.6V)
INDUSTRIAL UNITS MIN MAX 50 3 8 18 MIN MAX 52 3 8 19 1 1 1 2.2 VSS - .5 2.4 0.4 0 70 -40 0.4 85 VCC + .5 0.8 mA mA mA mA mA A A V V V V C tAVAV = 35ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 35ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA NOTES
PARAMETER Average VCC Current Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 3.3V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature 2.2 VSS - .5 2.4
ICC3b ISB1d ISB2d IILK IOLK VIH VIL VOH VOL TA
1 1 1 VCC + .5 0.8
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
3.3V
317 Ohms OUTPUT 351 Ohms
CAPACITANCEe
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 5 7 UNITS pF pF CONDITIONS
V = 0 to 3V V = 0 to 3V
30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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STK16C88-3
SRAM READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAV
f
(VCC = 3.0V-3.6V)
STK16C88-3-35 UNITS MIN MAX 35 35 35 15 5 5 13 0 13 0 35 ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
tAVQVg tGLQV tAXQXg tELQX tEHQZ tGLQX tGHQZ
h h
tHZ tOLZ tOHZ tPA tPS
tELICCHe tEHICCL
d, e
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT)
DATA VALID
3 tAVQV
SRAM READ CYCLE #2: E Controlledf
2 tAVAV ADDRESS 6 E tELQX 7 tEHQZ 1 tELQV 11 tEHICCL
G 4 8 tGLQX DQ (DATA OUT) 10 tELICCH
ACTIVE STANDBY
tGLQV
9 tGHQZ
DATA VALID
ICC
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STK16C88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ tWHQX
h, i
(VCC = 3.0V-3.6V)
STK16C88-3-35 PARAMETER UNITS MIN MAX ns ns ns ns ns ns ns ns 13 5 ns ns 35 25 25 12 0 25 0 0
#2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ
PREVIOUS DATA DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
DATA OUT
HIGH IMPEDANCE
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledj
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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STK16C88-3
AutoStorePlusTM/POWER-UP RECALL
SYMBOLS NO. Standard 22 23 24 25 tRESTORE tstg VSWITCH VRESET Power-up RECALL Duration Minimum VCC Slew Time to Ground Low Voltage Trigger Level Low Voltage Reset Level 500 2.7 2.95 2.4 PARAMETER MIN MAX 550 s ns V V e k e, g
(VCC = 3.0V-3.6V)
STK16C88-3 UNITS NOTES
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
AutoStorePlusTM/POWER-UP RECALL
VCC
3.3V 24 VSWITCH 25 VRESET
23 tstg
AutoStoreTM 31 tSTORE POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStorePlusTM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStorePlusTM RECALL WHEN VCC RETURNS ABOVE VSWITCH
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SOFTWARE STORE/RECALL MODE SELECTION
E W A13 - A0 (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63 MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z NOTES
L
H
l, m
L
H
l, m
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK16C88-3, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEn, o
NO. 26 27 28 29 30 31 SYMBOLS tAVAV tAVEL
n n
(VCC = 3.0V-3.6V)
STK16C88-3-35 UNITS MIN MAX ns ns ns ns 20 10 s ms 35 0 25 20
PARAMETER STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Cycle Duration STORE Cycle Duration
tELEH tELAX
g, n
tRECALL tSTORE
Note n: The software sequence is clocked with E controlled reads. Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
tAVAV ADDRESS
27 ADDRESS #1 26
tAVAV
ADDRESS #6
26
tAVEL E
tELEH
28
tELAX
31 30 / tRECALL
29
tSTORE DQ (DATA
DATA VALID DATA VALID
HIGH IMPEDANCE
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DEVICE OPERATION
The AutoStorePlusTM STK16C88-3 is a fast 32K x 8 SRAM that does not lose its data on power-down. The data is preserved in integral QuantumTrapTM Nonvolatile Elements while power is unavailable. The nonvolatility of the STK16C88-3 does not require any system intervention or support: AutoStorePlusTM on power-down and automatic RECALL on power-up guarantee data integrity without the use of batteries.
AutoStorePlusTM OPERATION
The STK16C88-3's automatic STORE on powerdown is completely transparent to the system. The AutoStoreTM initiation takes less than 500ns when power is lost (VCC < VSWITCH) at which point the part depends only on its internal capacitor for STORE completion. If the power supply drops faster than 20s/volt before Vccx reaches Vswitch, then a 2.2 ohm resistor should be inserted between Vccx and the system supply to avoid a momentary excess of current between Vccx and Vcap. In order to prevent unneeded STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place.
NOISE CONSIDERATIONS
Note that the STK16C88-3 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM READ
The STK16C88-3 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high.
POWER-UP RECALL
During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK16C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10k resistor should be connected either between W and system VCC or between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK16C88-3 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
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To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
tile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK16C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCC < VSWITCH, all software STORE operations and SRAM WRITEs are inhibited.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
LOW AVERAGE ACTIVE POWER
The STK16C88-3 draws significantly less current when it is cycled at times longer than 55ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK16C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/ O loading.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvola50
50
Average Active Current (mA)
Average Active Current (mA)
40
40
30
30 TTL CMOS 10
20 TTL 10 CMOS 0 50 100 150 Cycle Time (ns) 200
20
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
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STK16C88-3 ORDERING INFORMATION
STK16C88-3 W F 35 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
35 = 35ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
W = Plastic 28-pin 600 mil DIP
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STK16C88-3
Document Revision History
Revision 0.0 0.1 0.2
Date December 2002 September 2003 March 2006
Summary Added lead-free lead finish Removed 45ns and 55ns speed grades, Removed Leaded lead finish.
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STK16C88-3
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